Location: Newark, CA 94560
Type: Contract
JO#: 25-08288:CD
Title: Onsite Mid-level Verification Engineer, UVM, SystemVerilog
Description:
Onsite Mid-level Verification Engineer with 5-8 years of experience of pure verification in FPGA.
This is a pure Verification Engineer only role.
This position is onsite in the greater San Jose Bay Area .
What you will be doing:
What you will need:
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